Get Step By Step Guide To Implementing The Cortex-m0 ... - Latech

Differences between the Cortex-M3 and -M0 The Cortex-M3 processor is based on the ARMv7-M architecture. It supports many more 32bit Thumb instructions and a number of extra system features. The performance of the CortexM3 is also higher than that for the Cortex-M0.

Compared with Cortex-M0+, Cortex-M4 performance is about 6 times higher performance. Also, because Cortex-M0+ adopted the 2 stage pipeline, it would not get such faster clock speed as Cortex-M4.

The processor implements the ARMv6-M Thumb instruction set, including a number of 32-bit instructions that use Thumb-2 technology. The ARMv6-M instruction set comprises: all of the 16-bit Thumb instructions from ARMv7-M excluding CBZ , CBNZ and IT.

Cortex-M1 runs a subset of the Thumb-2 instruction set (ARMv6-M) that includes all base 16-bit Thumb instructions and a few Thumb-2 32-bit instructions (BL, MRS, MSR, ISB, DSB, and DMB).

Arm® Cortex®-M0 in a nutshell The Arm® Cortex®-M0 is the smallest Arm® processor available, with a very small silicon area, low gate count, low power and minimal code footprint. Suitable for analog and mixed signal devices, it allows microcontroller suppliers to offer 32-bit performance at 16- and 8-bit price points.

The Cortex-M0 processor supports different data types by providing various memory access instructions for different transfer sizes and by providing a 32-bit AHB-LITE interface, which supports 32-bit, 16-bit, and 8-bit transfers.

The ARM instruction sets. The ARMv7 architecture is a 32-bit processor architecture. It is also a load/store architecture, meaning that data-processing instructions operate only on values in general purpose registers. Only load and store instructions access memory.

Instruction set summary The processor implements the ARMv6-M Thumb instruction set, including a number of 32-bit instructions that use Thumb-2 technology. The ARMv6-M instruction set comprises: All of the 16-bit Thumb instructions from ARMv7-M excluding CBZ , CBNZ and IT.